1. Field of the Invention
This invention relates to the field of synchronization of phase mismatch in communication systems employing clocks having a common period. More particularly, the present invention relates to methods and devices for recovering from a metastable state in potentially phase-mismatched communication systems employing a common clock period.
2. Description of the Related Art
Current trend in personal digital assistants, personal communications systems and portable computing devices, peripherals and organizers point to the growing popularity of wireless communications. In particular, many consumer products now have the ability to communicate with other devices by means of, for example, RF or infrared data transfer. For some applications, infrared communications has many advantages not possessed by other data transfer modalities. Infrared communication devices are inexpensive, compact, have wide bandwidth and are highly secure, as infrared transceivers are typically limited by both line of sight and by short distance. In such wireless communications systems, the transfer speed may be predetermined or may be contemporaneously negotiated between the communicating devices.
To promote interoperability, many wireless communications protocols have been standardized across manufacturers of wireless communications devices. One such standard-setting organization is the Infrared Data Association (http://www.irda.org), which promulgates standards for infrared communications. For example, according to the Serial Infrared Link Access Protocol (IrLAP) version 1.1 (incorporated herein by reference in its entirety), the initial baud rate between any two IrLAP-compliant devices is set at 9600 bits per second (bps) during a discovery or contention stage, with the provision of a fall-back speed of 2400 bps. During this stage, the two devices attempt to communicate predetermined bit sequences to ascertain the maximum data rates sustainable by both devices. According to IrLAP ver. 1.1, the transmitting device transmits data packets including a series of predetermined bit sequences (called a preamble) to the other device. The other device then attempts to recover the transmitted preamble. However, there are occasions when the receiving clock cannot be synchronized to the timing of the incoming data from the transmitting device, resulting in failed communications and no data transfer between the two devices. This may occur, for example, when the transmitting and receiving clocks are metastable relative to one another. Metastability refers to the state wherein an active clock edge and a data transition occur very close to one another. Such a metastable situation is depicted in FIG. 1.
In the timing diagram of FIG. 1, the transmitting device transmits data (a digital bit string of xe2x80x9c1010xe2x80x9d in the example of FIG. 1) according to a transmitter clock, which is active high. That is, the state changes (data transitions) occur at or very close to the rising edges of the transmitter clock pulses. The receiver device attempts to acquire the data sent by the transmitting device by timing the sampling of the data also on the rising edge of its clock, as shown in FIG. 1. Both transmitting and receiving devices in FIG. 1 operate on respective active high clock signals. Moreover, both the transmitter clock and the receiver clocks signals have a constant and equal period. Indeed, the transmitter and receiver devices, in FIG. 1, have previously negotiated a common data rate with period 1/f, or the frequency f may have been protocol-mandated as the single common frequency at which data is to be exchanged. For example, according to the IrLAP protocol, both infrared devices may be configured to initially exchange data at the common rate of 9600 bps.
The first data bit shown begins its transition form a low voltage value to a high voltage value at the rising edge of the first transmitter clock pulse shown. However, the receiver clock is not synchronized to the transmitter clock. Most of the time, this lack of synchronism between the transmitter and receiver clocks can be overcome and the data can be successfully acquired, latched and recognized. There is at least one situation, however, in which the flip-flop or latch acquiring the data bit string from the transmitting device cannot properly transition from its current state into the new state. This may occur when an active clock edge and a data transition occur very close together, as shown in FIG. 1. Indeed, the phase differential 10 between the transmitter clock and the receiver clock may be such that the active edge of the receiver clock occurs between the high and low voltage threshold magnitudes VLT and the VHT. The low voltage threshold magnitude VLT and the high voltage threshold magnitude VHT may be defined as that voltage below and above which, respectively, a logical low state and logical high state value will be recognized. The manufacturer of the device in question typically does not warrant the behavior of the device between these threshold values, as device is in an indeterminate state, transitioning between a logical 0 and a logical 1. Should the active edge of the receiver clock, as shown in FIG. 1, occur at about the same time 20 as the data is transitioning (or anywhere within the interval between the timing of VLT and the VHT), the receiver device may not be able to accurately recognize the data transmitted by the transmitter device. At time 20, the receiver may recognize a logical one, a logical zero, fluctuate between the two states or merely exhibit an increased time to output. The receiver device is then in a metastable state. In such a state, the latch or flip flop in the receiver may not immediately transition from its current state to a new state, as the new state is dictated by the transmitted data, which is itself sampled during a state transition. Moreover, this state is xe2x80x9cstablexe2x80x9d, in that the receiver will continue to sample the transmitted data indefinitely just when the data is transitioning, as the period of the receiver clock is constant and equal (or substantially equal) to that of the transmitting device. This is shown at reference numeral 30 in FIG. 1, in which the third active edge of the receiver clock samples the transmitted data once again between VLT and the VHT.
FIG. 2 is a conceptual diagram illustrating metastability. As shown therein, a metastable state VM may be likened to the state of a ball atop a hill. The ball, in this state, may roll in either one of two directions to rest either in a stable low state VL or in a stable high state VH. The metastable state VM itself, however, is an indeterminate state, neither a logical high nor a logical low. Noise may eventually change the state of the ball from the metastable state to either of the stable states. However, before such change of state occurs, the state of the ball remains indeterminate. In digital sequential circuits, such a metastable state may cause the output of the flip-flop or latch within the receiver to oscillate or to itself assume an indeterminate state.
Such a metastable state, therefore, will persist for an indefinite period of time unless remedial action is undertaken. It is thus desirable to remedy such a metastable condition. Conventionally, the solution is to reset either the transmitter or the receiver or to somehow change the phase differential 10 between their respective clocks. As the phase differential 10 during which metastability may occur is fairly small, it is likely that cycling either or both of the transmitter and receiver devices on and off will solve the problem, as the active edges of the receiver clock are somewhat unlikely to consecutively reappear just during the interval in which the data is transitioning states. Another way to get out of a metastable state is to sample at a much higher rate (greater than two times, for example) than the rate at which the data is sent. Such solutions, however, are believed to be less than optimal, as it may require the user(s) of the devices to reset the device(s) or to turn the device(s) on and off before re-attempting any data transfers or may require an overly high sampling rate. What are needed, therefore, are devices and methods for recovering from a metastable state in phase-mismatched communication systems employing a common clock period.
The principles of the present invention provide for devices and methods that are able to recover from such a metastable state.
A device to overcome a metastable state in a communication system employing a common clock period, according to an embodiment of the present invention, comprises a first latch and a second latch, the first latch being clocked by a clock signal and the second latch being clocked by an inverted version of said clock signal, each of the first and second latches receiving a data stream; a delay device, the delay device delaying an output of the second latch by one half of a cycle of said clock signal; and a multiplexer, said multiplexer outputting said output of said first latch when said received data stream does not exhibit metastability relative to said clock signal and outputting an output of said delay device in a presence of metastability.
A sequence recognizer may be included, the sequence recognizer being configured to recognize a predetermined bit sequence on the output of the first latch and to control the multiplexer to output the output of the delay device upon failing to detect the predetermined bit sequence. The delay device may include a latch clocked by the clock signal.
The present invention may also be viewed as a method of receiving a data signal in a communication system wherein both transmitter and receiver employ a common clock period, comprising a first acquiring step of acquiring the data signal on respective first active edges of a clock signal; detecting a presence of metastability relative to said respective first active edges and said data signal; a second acquiring step of acquiring said data signal on respective second active edges of said clock signal; and synchronizing said data signal acquired on said respective second active edges with said first active edges.
The respective first active edges may be rising edges of the clock signal and the respective second edges may be falling edges of the clock signal. Alternatively, the respective first active edges may be falling edges of the clock signal and the respective second edges may be rising edges of the clock signal. The first acquiring step may include a step of latching the data signal in a first latch clocked by the clock signal. The second acquiring step may include a step of latching the data signal in a second latch clocked by an inverted version of the clock signal. A step of outputting the data signal acquired on the respective first active edges of said lock signal may be carried out when metastability is not detected. A step of outputting the synchronized data signal may be carried out when metastability is detected. The detecting step may include a step of recognizing a selected bit sequence, the metastability being inferred upon failure of the recognizing step to recognize said predetermined bit sequence. The synchronizing step may include a step of delaying the data signal acquired on the respective second active edges by one half cycle of the clock signal. The first and second acquiring steps may be carried out concurrently.
The present invention is also a transceiver, comprising means for transmitting data according to a clock signal having a period; means for receiving data, including first means for acquiring data on respective first active edges of a clock signal having said period; means for detecting a presence of metastability relative to said respective first active edges and said data; second means for acquiring said data on respective second active edges of said clock signal; means for synchronizing said data acquired on said respective second active edges with said first active edges; and means for outputting said data acquired on said respective first active edges when metastability is not detected and outputting said synchronized data when metastability is detected.
The transmitting means and the receiving means each may include an infrared device. The synchronizing means may include means for delaying the data for half of cycle of the clock signal. The detecting means may include means for detecting the presence of a predetermined bit sequence in the acquired data. The respective first active edges may be rising edges of the clock signal and the respective second edges may be falling edges of the clock signal. Alternatively, the respective first active edges may be falling edges of the clock signal and the respective second edges may be rising edges of the clock signal. The first acquiring means may include first latching means for latching the data, the first latching means being clocked by the clock signal. The second acquiring means may include second latching means for latching the data, the second latching means being clocked by an inverted version of the clock signal.